How Many Registers Can Referred By Register Specifier?

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two.three Registers

The 80386 contains a total of sixteen registers that are of interest to the applications programmer. As Effigy 2-5 shows, these registers may be grouped into these bones categories:

1. General registers. These eight 32-bit general-purpose registers are used primarily to contain operands for arithmetics and logical operations.
2. Segment registers. These special-purpose registers let systems software designers to choose either a flat or segmented model of memory organization. These six registers determine, at any given time, which segments of memory are currently addressable.
3. Status and pedagogy registers. These special-purpose registers are used to record and alter certain aspects of the 80386 processor state.

two.3.1 General Registers

The full general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. These registers are used interchangeably to contain the operands of logical and arithmetic operations. They may besides exist used interchangeably for operands of address computations (except that ESP cannot exist used as an alphabetize operand).

As Effigy two-v shows, the low-order give-and-take of each of these viii registers has a divide name and can exist treated as a unit. This feature is useful for handling sixteen-bit data items and for compatibility with the 8086 and 80286 processors. The word registers are named AX, BX, CX, DX, BP, SP, SI, and DI.

Figure 2-5 also illustrates that each byte of the 16-chip registers AX, BX, CX, and DX has a separate proper noun and tin can be treated as a unit. This feature is useful for handling characters and other eight-fleck data items. The byte registers are named AH, BH, CH, and DH (loftier bytes); and AL, BL, CL, and DL (depression bytes).

All of the full general-purpose registers are available for addressing calculations and for the results of about arithmetic and logical calculations; however, a few functions are dedicated to sure registers. Past implicitly choosing registers for these functions, the 80386 architecture tin encode instructions more compactly. The instructions that use specific registers include: double-precision multiply and divide, I/O, cord instructions, translate, loop, variable shift and rotate, and stack operations.

ii.3.2 Segment Registers

The segment registers of the 80386 requite systems software designers the flexibility to cull among various models of memory organization. Implementation of memory models is the bailiwick of Part II -- Systems Programming. Designers may choose a model in which applications programs practise not need to modify segment registers, in which example applications programmers may skip this section.

Complete programs more often than not consist of many dissimilar modules, each consisting of instructions and data. Nevertheless, at any given time during program execution, but a modest subset of a plan's modules are actually in use. The 80386 architecture takes reward of this by providing mechanisms to support direct admission to the instructions and information of the current module's environment, with admission to additional segments on demand.

At whatsoever given instant, six segments of retentivity may be immediately attainable to an executing 80386 plan. The segment registers CS, DS, SS, ES, FS, and GS are used to identify these six current segments. Each of these registers specifies a item kind of segment, as characterized by the associated mnemonics ("code," "data," or "stack") shown in Effigy ii-6 . Each register uniquely determines ane particular segment, from among the segments that make upward the program, that is to be immediately accessible at highest speed.

The segment containing the currently executing sequence of instructions is known every bit the current code segment; information technology is specified by ways of the CS register. The 80386 fetches all instructions from this code segment, using as an offset the contents of the educational activity pointer. CS is changed implicitly as the outcome of intersegment control-transfer instructions (for example, Call and JMP), interrupts, and exceptions.

Subroutine calls, parameters, and procedure activation records usually require that a region of memory be allocated for a stack. All stack operations use the SS register to locate the stack. Different CS, the SS register can be loaded explicitly, thereby permitting programmers to define stacks dynamically.

The DS, ES, FS, and GS registers allow the specification of four data segments, each addressable past the currently executing plan. Accessibility to four carve up data areas helps programs efficiently admission different types of data structures; for example, i data segment annals can point to the data structures of the current module, some other to the exported data of a higher-level module, another to a dynamically created data construction, and another to data shared with another job. An operand within a information segment is addressed by specifying its commencement either directly in an instruction or indirectly via general registers.

Depending on the structure of data (e.k., the way data is parceled into one or more than segments), a program may require access to more than than four information segments. To admission boosted segments, the DS, ES, FS, and GS registers can be changed nether programme control during the course of a program's execution. This simply requires that the program execute an instruction to load the appropriate segment register prior to executing instructions that access the information.

The processor associates a base address with each segment selected past a segment annals. To address an element inside a segment, a 32-chip offset is added to the segment's base address. In one case a segment is selected (past loading the segment selector into a segment register), a data manipulation instruction only needs to specify the beginning. Simple rules ascertain which segment register is used to grade an accost when just an offset is specified.

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2.iii.3 Stack Implementation

Stack operations are facilitated by iii registers:

1. The stack segment (SS) annals. Stacks are implemented in memory. A system may have a number of stacks that is express only by the maximum number of segments. A stack may be up to four gigabytes long, the maximum length of a segment. Ane stack is straight addressable at a -- 1 located by SS. This is the current stack, often referred to simply as "the" stack. SS is used automatically by the processor for all stack operations.
2. The stack arrow (ESP) register. ESP points to the top of the push-down stack (TOS). It is referenced implicitly by Push and Pop operations, subroutine calls and returns, and interrupt operations. When an particular is pushed onto the stack (see Effigy two-vii ), the processor decrements ESP, then writes the detail at the new TOS. When an particular is popped off the stack, the processor copies information technology from TOS, then increments ESP. In other words, the stack grows down in memory toward lesser addresses.
3. The stack-frame base of operations pointer (EBP) register. The EBP is the best option of register for accessing information structures, variables and dynamically allocated piece of work space within the stack. EBP is frequently used to admission elements on the stack relative to a fixed signal on the stack rather than relative to the current TOS. It typically identifies the base address of the current stack frame established for the current procedure. When EBP is used every bit the base register in an kickoff calculation, the offset is calculated automatically in the current stack segment (i.e., the segment currently selected past SS). Because SS does non have to exist explicitly specified, instruction encoding in such cases is more than efficient. EBP tin also exist used to index into segments addressable via other segment registers.

2.3.iv Flags Annals

The flags register is a 32-chip register named EFLAGS. Figure 2-eight defines the bits within this annals. The flags control certain operations and indicate the condition of the 80386.

The low-order 16 bits of EFLAGS is named FLAGS and tin can be treated as a unit. This feature is useful when executing 8086 and 80286 lawmaking, because this role of EFLAGS is identical to the FLAGS register of the 8086 and the 80286.

The flags may be considered in 3 groups: the condition flags, the control flags, and the systems flags. Discussion of the systems flags is delayed until Role II.

2.3.4.one Status Flags

The status flags of the EFLAGS register allow the results of one instruction to influence later on instructions. The arithmetic instructions use OF, SF, ZF, AF, PF, and CF. The SCAS (Scan String), CMPS (Compare String), and LOOP instructions employ ZF to signal that their operations are complete. There are instructions to set, clear, and complement CF before execution of an arithmetics instruction. Refer to Appendix C for definition of each condition flag.

ii.3.4.2 Control Flag

The control flag DF of the EFLAGS register controls string instructions. DF (Direction Flag, bit 10) Setting DF causes cord instructions to machine-decrement; that is, to process strings from high addresses to low addresses. Clearing DF causes string instructions to auto-increment, or to process strings from low addresses to loftier addresses.

2.3.4.3 Instruction Pointer

The educational activity pointer register (EIP) contains the first address, relative to the first of the electric current code segment, of the next sequential instruction to exist executed. The instruction arrow is not directly visible to the programmer; it is controlled implicitly by control-transfer instructions, interrupts, and exceptions.

As Effigy two-9 shows, the depression-social club sixteen bits of EIP is named IP and can exist used by the processor equally a unit. This feature is useful when executing instructions designed for the 8086 and 80286 processors.

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Source: https://pdos.csail.mit.edu/6.828/2004/readings/i386/s02_03.htm

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